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In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog. ==History== SystemVerilog started with the donation of the Superlog language to (Accellera ) in 2002.〔Rich, D. “The evolution of SystemVerilog” IEEE Design and Test of Computers, July/August 2003〕 The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005.〔(IEEE approves SystemVerilog, revision of Verilog )〕 In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009. The current version is IEEE standard 1800-2012.〔()〕 The feature-set of SystemVerilog can be divided into two distinct roles: # SystemVerilog for RTL design is an extension of Verilog-2005; all features of that language are available in SystemVerilog. # SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog. The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「SystemVerilog」の詳細全文を読む スポンサード リンク
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